Wire bonds, physically, as well as electrically, connected to underlying circuitry, of semiconductor chips, are used to connect the specific semiconductor chip to packaging elements, such as printed circuit board, or ceramic modules. Bond pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bond pads are required to transmit power/ground and input/output signals to the chip devices. It is thus important that reliability of bond pad be sufficiently high to ensure high yield. The general bond pad consists of metal layers separated by inter-metal dielectric (IMD) layers and metal vias passing the IMD layers for electrically connecting the metal layers. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection. Wires are bonded to the bond pad and to the chip package forming electrical connections between the chip and the package.
In most cases metal vias are patterned as an array of grids in the IMD layer underlying an uppermost metal layer. The large, exposed, surface area of IMD layer, however, located surrounding the smaller regions of metal vias, can result in defect formation, or cracking of the IMD layer, as a result of the large bonding force, experienced during the wire bondingtests, where the large bonding force is distributed throughout the overlying bond pad. A significant failure mode involves cracking of the IMD layer. Once a small crack is initiated to propagate along the IMD layer, under stresses it will grow extensively during subsequent processes. One approach for eliminating the cracks, the top metal via is designed as a mesh pattern. Such a mesh via pattern is often formed or deposited in a manner that can't fully fill holes to provide poor coverage on intersection areas where line vias cross with each other, mainly because of a marginal photolithography process window induced by circuits under pad (CUP) layout. This impacts reliability, bondability and quality control (QC) results, and the yield impact may reach 10˜15% depending on variations in chip size. In order to avoid problems in devices that could arise from non-fully filled metal vias, design rules do not allow integrated circuits to underlie the bond pad.